Designing an integrated circuit involves considering factors that relate to electronic circuits, analog functions, logic, and other functionality. For example, before it is released for production (i.e., tape out), an integrated circuit device may undergo a series of simulation tests to ensure that the integrated circuit will operate as planned. These simulation tests can be used to find bugs, mistakes, or other issues with the device. This simulation is referred to as design verification.
Design verification can provide several benefits. For example, design verification can reduce the need for tape out processes that can be expensive and time consuming, which can prolong the time it takes to bring the device to market. That is because the design verification environment can simulate and/or emulate the bugs and other problems that would otherwise be found by the end customers, thereby allowing the design team to fix the problems before significant time and money is sunk into production. Examples of devices that can benefit from the verification process include memory devices, communication circuitry, modems, smart phones, and field programmable gate arrays, among others.
This verification process can involve several engineers collaborating in a combined effort to check and test multiple circuits under various circumstances and operating environments. Universal Verification Methodology (UVM) is a standardized protocol designed to help unify techniques for verifying integrated circuit designs. UVM provides a library of automation features that are compatible with the SystemVerilog language and can include, for example, sequences and data automation features such as packing, copy, compare, and the like.
UVM provides a common framework for developing verification environments across various platforms and circumstances. However, using UVM still requires manual coding, which can be a time consuming and laborious task. This manual coding process can last from few working days to few working weeks. Manually written environments are also error-prone and do not always follow the methodology. Furthermore, their structure can vary within the same project, which makes the maintenance, reuse and hand-over difficult.